Gate arrays are used in VLSI integrated circuit chips to implement MOSFET circuits in semiconductor wafers. An MOS gate array consists of an array of MOS transistor sources and drains separated by channels, above which are formed gates to control the conductivity of the channels and thus the state of the transistors. An array of these gates (and their sources and drains) becomes functional only when connected by conductive wiring to appropriate other elements Generally, the connecting is accomplished in two steps: a library of macrocells is available to translate simple frequently used logic functions such as NAND, flip-flop, ADD, multiplexer, and counter into a gate array wiring pattern, then the macrocells are connected together to form the complex logic function of the VLSI chip.
Although conceptually there are two steps, the actual metallization to accomplish the two steps is laid out in as few layers as possible, preferably two, so the metal to implement a single macrocell and the metal to connect macrocells to each other is in the same metallization layers. Therefore if an area in a metal layer is used for connecting points within a macrocell, it is not also available for connecting macrocells to each other.
There has been considerable interest in implementing complex logic operations on smaller areas of semiconductor material, while simultaneously retaining the flexibility provided by a gate array in which identical structural units repeat throughout a large portion of the semiconductor area. A gate array structure consists generally of a base array of many active areas which can be fabricated as a standard product on which is formed one or more "personality layers" comprising conductive material to interconnect the active areas into a desired logical structure. The personality layers reflect the function or functions to be B implemented by the finished array. A given base array can be used to implement many different functions by appropriately designing the personality layers. Thus a gate array allows many different logic functions to be implemented using the same base array. The geometry of the base array cell affects the ability of the designer using later metallization to achieve a final product having maximum density and performance.
FIG. 1 shows a partial schematic diagram of a typical prior art layout for an HCMOS logic array. Column Cl lB contains a plurality of n-channel active areas denoted by Nll, N21, N31....Nk1...NK1 formed in a p-well where K is an integer representing the number of elements (such as HCMOS transistors) in the column and k is an integer given by 1.ltorsim.k.ltorsim.K. Column C2 contains a plurality of p-channel active areas P12, P22, P32...Pk2...PK2 formed in an n-type substrate. In general, the odd columns Cl, C3, C5, etc. contain n-channel active areas for forming n-channel transistors and the even columns C2, C4, etc. contain p-channel active areas for forming p-channel transistors. The columns are arranged in pairs each pair containing a column of n-channel active areas and a column of p-channel active areas. Each column also contains a plurality of K p+ well taps such as column 1 well taps T11, T21, T31, ...Tk1...TK1 or n+ substrate taps T12, T22, T32, ...Tk2...TK2 for connecting metal to the substrate or well. For example, tap Tll in column Cl is a p+ p-well tap and tap T12 in column C2 is an n+ substrate tap.
The pairs of columns are separated by dedicated routing channels Rl, R2, etc. Each routing channel contains space for a fixed number of leads, called routing tracks, running on top of oxide isolation regions formed between the pairs of columns. In the interest of standardization and flexibility in implementing multiple functions with the same substrate layout, the same number of routing tracks is allocated to each routing channel within the array. The routing tracks are shown schematically in FIG. 1 by unnumbered parallel lines in each routing channel. Metallization (not shown) is formed above the active areas B in a particular pair of columns to connect elements within a macrocell and the routing tracks are used to provide the electrical interconnections between selected macrocells to implement the VLSI circuit.
The width of a routing channel depends on the number of routing tracks in the channel. In conventional gate array technology, the number of routing tracks per channel, typically 16 to 26, is chosen to provide good routability and typically increases with array size. This is satisfactory for many designs, but may lead to either an excess of tracks or to an under-utilization of the active areas in various pairs of columns. On the one hand, if the number of routing tracks per channel is sufficiently high to accommodate the traffic demands in a congested area of the chip then there is typically an excess of routing tracks in less congested areas of the chip with an attendant waste of silicon area. On the other hand, if the number of routing tracks allocated per channel is not enough to accommodate the desired interconnections for complex macrocells, then there is a waste of silicon area in regions where all adjacent routing tracks are already used or the interconnections must detour through other routing channels or use second metal. Either alternative is unsatisfactory. Detours are unsatisfactory because the increased conductor length increases capacitance and reduces speed. Use of a second conductive layer negates the simplicity of implementation provided by the dedicated routing channels. An insufficient number of routing tracks per channel also makes 100% auto-routing as provided by computer-aided design difficult to achieve in most designs.
The prior art layout shown in FIG. 1 has an additional disadvantage in that the use of dedicated routing channels alternating with pairs of transistor columns generally limits the width of the macrocell to the width of a single pair of columns. For complex macrocells, this leads to a very large height to width aspect ratio which is undesirable since wiring between parts of one macrocell would have to B extend a long distance within a single pair of columns, adding unwanted capacitance and reducing speed. Alternatively, if a large macrocell is implemented in more than one pair of columns, the wiring to connect with an adjacent pair of columns must span the width of one or more routing channels. Since the spanned routing channels are not used for either active areas or routing between macrocells, that routing channel area is wasted.
FIG. 2a shows another prior art layout (not intended for field effect transistor technology) which provides a regular lB pattern of cells in a substrate area and dedicates no substrate area to routing channels. This layout may be used to form integrated circuit structures by providing at least two conductive layers above the substrate for personalized connections. Personalized connections may be made between active areas of the substrate in order to form simple logic gates and also to combine these simple logic gates to form complex functions on a single chip. One such device is described by Balyoz et al. in U.S. Pat. No. 4,249,193. FIG. 2b shows an inverter circuit to be implemented with this layout, as taught by Balyoz, and FIGS. 2c and 2d, show the substrate layout and metallization to implement the inverter circuit of FIG. 2b. The particular inverter circuit of FIG. 2b feeds multiple output points through Schottky diodes D1 through D6. These multiple contact points are labeled in FIGS. 2c and 2d. Ground and +V lines are shown as formed in first metal and running vertically through the structure while the metallization to connect to input point 11 and to output lines D1 through D6 is not shown.
While the geometry of FIG. 2a benefits over the geometry of FIG. 1 in not being restricted by fixed routing channels, the particular substrate areas of FIG. 2a have an orientation that serves only a few types of circuits. For example, the geometry of FIG. 2a having strips of active areas for forming bipolar transistors interposed with resistive strips is useful for the circuit of FIG. 2b but not for CMOS circuits. A prior art bipolar substrate geometry cannot be directly adapted for field effect transistor applications because of the need to accommodate formation of gates and channels. Further, a particular geometry for the formation of CMOS or HCMOS devices and for allowing maximum flexibility in implementing circuits using automatic routing with computer aided design is needed.
Reference is made to "A 4.1K Gates Double Metal HCMOS V 14 Sea of Gates Array" by A. Hui, A. Wong, C. Dell'Oca, D. Wong, and R. Szeto, Proceedings, IEEE 1985 Custom Integrated Circuits Conference, pages 15-16: and to "High Performance 129K Gate CMOS Array" by Tony Wong, Alex Hui, lB Daniel Wong, Teruo Kobayashi, Hiroaki Suzuki and Kinji Yamasaki, Proceedings of May 1986 Custom Integrated Circuits Conference, Rochester, N.Y. which provide background to understanding this invention and are incorporated herein by reference.
There has recently been an increased use of CMOS circuitry because of the extremely low current requirements of CMOS devices. Therefore, particularly useful is a gate array layout that provides maximum density of active devices in a CMOS or HCMOS circuit. A CMOS circuit uses both p-channel and n-channel MOSFET transistors in series.
A gate array geometry that particularly accommodates adjacent formation of p-channel and n-channel transistors with CMOS transistors in an optimum circuit layout with minimum waste of silicon area and simultaneously allows for efficient implementation of large macrocells is desired.